Projects
Hardware, architecture and side projects
Hardware & Architecture
SS16: 16-bit superscalar processor
In-order superscalar core in SystemVerilog with a two-pass assembler, a golden instruction-set simulator and an automated co-simulation regression. Out-of-order extension (rename, ROB, issue queue) in progress.
6-stage pipelined RISC processor and SAT-based ATPG
Full datapath with forwarding and interlocks in VHDL, plus SAT-based ATPG for the 74181 ALU that cut ATPG effort 3.67×.
FHSS secure transmission with a hardware LWE engine
Learning-With-Errors encryption core on a PYNQ-Z2, interfaced over AXI-Lite and AXI-DMA for a 12.87× speedup over software, with frequency hopping through a custom GNU Radio module on a USRP.
Microarchitectural side-channels on RISC-V out-of-order cores
Reproduced Spectre-class cache and prefetcher side-channel primitives on a RISC-V out-of-order core, with the toolchain and full-system gem5 + Chipyard flow built end to end.
ML-driven LLC partitioning for CPU-GPU SoCs
Hardware perceptron that predicts per-core cache sensitivity to set LLC way-masks every 1M cycles, gaining 8.36% on CPU at a 7.5% GPU cost over a static split. Instrumented gem5 for the motivating results.
Spiking neural networks and compute-in-memory
Compared supervised deep SNNs with unsupervised STDP on MNIST (93.8% for the supervised model) and evaluated compute-in-memory inference in SpikeSim on a 64×64 crossbar at 65 nm.
RTL-to-GDSII sequential MAC
16×16 shift-and-add multiplier taken through the full OpenLane flow on SkyWater sky130, closing at 5.53 ns setup with zero DRC violations and clean LVS. 6× smaller and 19× lower power than a parallel FIR.
Side Projects
Public repositories from github.com/Prayag-Mohanty.
badminton-scoreboard
Upload a match recording and get a scoreboard tracking the players' points through the match.