Research
GPU architecture and memory systems
Address Translation for Multi-Chip-Module GPUs
M.Tech thesis, advised by Prof. Virendra Singh. Investigating virtual-memory translation as a bottleneck when the TLB and page-walk hierarchy is split across dies. Proposes coupling TLB and cache replacement through dead-page prediction at the L1 TLB, prototyped on the MGvm MCM-GPU simulator. Targeting a conference submission by mid-2027.
Locality-Aware Victim Cache for GPGPU L1 Data Caches
Co-designed a victim cache held in underused register-file capacity, with a warp scheduler that favours warps whose working set is still resident, so retained L1D lines are re-referenced before eviction. Implemented end to end in GPGPU-Sim on an NVIDIA Volta GV100 configuration for a 1.042× IPC gain over baseline. Presented as a poster at the Indo-Japanese Workshop on Trustable Cyber-Physical Cognitive Systems, IIT Bombay (2026).
Out-of-Order Scheduling for GPUs
M.Tech seminar. Surveyed seven out-of-order GPU proposals from ISCA, HPCA, TPDS and TACO (2016–2024), tabulating performance, power and area trade-offs: 6.9–38% speedup for 0.007–13% power and 0.05–2.4% area. Showed that PTX-level simulation overstates available ILP, so SASS-level evaluation is the right baseline.
Publications
- Locality-Aware Victim Caching with Locality-Aware Warp Scheduling for GPUsP. Mohanty and V. Singh · IEEE International Conference on Computer Design (ICCD) 2026 · under review